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NCP1901 Advance Information Primary Side Combination Resonant and PFC Controllers
The NCP1901 is a combination of PFC and half-bridge resonant controllers optimized for off-line adapter applications. This device includes all the features needed to implement a highly efficient and small form factor adapter. It integrates a critical conduction mode (CrM) power factor correction (PFC) controller and a half-bridge controller with a built-in 600 V driver. The half-bridge stage operates at a fixed frequency. Regulation is achieved by adjusting the PFC stage output voltage. This device includes an enable input on the PFC feedback pin, open feedback loop protection and PFC overvoltage and undervoltage detectors. Other features included in the NCP1901 are a 600 V startup circuit and an adjustable frequency oscillator. The controllers are properly sequenced, simplifying system design. Adjustable Half-Bridge Frequency up to 75 kHz Open Feedback Loop Protection CrM Power Factor Correction Controller PFC Undervoltage Detector PFC Overvoltage Detector Half-Bridge Controller with 600 V High Side Gate Drive State Machine Ensures Proper Turn-on and Turn-off of Half-Bridge Stage Enable Input on the PFC Feedback Pin Disables Controllers and Reduces Power Controllers are Properly Sequenced for Fault Free Operation Internal 600 V Startup Circuit This is a Pb-Free Device
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SO-20 WB DW SUFFIX CASE 751D
SOIC-16 D SUFFIX CASE 751B
MARKING DIAGRAM
16 NCP1901G AWLYWW 1 20 NCP1901 AWLYYWWG
Features
* * * * * * * * * * *
1 NCP1901 = Specific Device Code A = Assembly Location WL = Wafer Lot Y or YY = Year WW = Work Week G = Pb-Free Package
ORDERING INFORMATION
Device NCP1901DR2G NCP1901DWR2G Package SOIC-16 (Pb-Free) SO-20 WB (Pb-Free) Shipping 2500/T ape & Reel 1000/T ape & Reel
Typical Applications
* High Efficiency Notebook Adapter * Solid State Lighting
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
(c) Semiconductor Components Industries, LLC, 2009
February, 2009 - Rev. P0
1
Publication Order Number: NCP1901/D
NCP1901
SO-20 WB HV 1 NC 2 NC 3 OSC 4 GND 5 VREF 6 PFB 7 PCS 8 PZCD 9 PControl 10 20 HBoost 19 HDRVhi 18 HVS 17 NC 16 NC 15 HDRVlo 14 PDRV 13 PGND 12 VCC 11 PCT HV OSC GND VREF PFB PCS PZCD PControl SOIC-16 1 HBoost HDRVhi HVS HDRVlo PDRV PGND VCC PCT
Figure 1. Pin Connections
VCC PDRV - + PZCD HV ZCD Comparator Istart UVLO VCC Good S Q Dominant Reset Latch Q R Level Shifter On time Comparator Level Shifter + - PFC OVP Comparator - + Pulse Trigger Delay Q Clock CLK Q Q Enable PDRV UVLO S R Q Delay Q CLK + - + 5V/ 3V - VDD IOSC(C) OSC 4*IOSC(C) VCC Management + - + - VCC(on)/ VCC(off)/ UVLO VCC CCC Dboost HBoost HDRVhi HVS VCC HDRVlo GND
VDD > 5.65 V Clamp < 2.25 V Clamp PFC Error Amplifier + -
+
PControl
VZCD
Undervoltage Detector S Dominant Reset Q Latch R
PFB
IPFB VDD IPCT(C)
+ -
VPREF
Cboost
PCT
+ PFC UVP VPOVP - Comparator + VPUVP - + - VCCGood
+ -
VPCS(ILIM)
+ -
PCS
LEB
PCS Comparator
VDD
Voltage Reference
VREF
Figure 2. Functional Block Diagram
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Table 1. PIN FUNCTION DESCRIPTION
20 Pin 1 16 Pin 1 Name HV Description This is the input of the high voltage startup regulator and connects directly to the bulk voltage. A constant current source supplies current from this pin to the VCC capacitor, eliminating the need for an external startup resistor. The charge current is 7.5 mA (typical). A capacitor on this pin adjusts the frequency of the internal oscillator. The oscillator sets the frequency of the half-bridge controller. The half-bridge operates at half the oscillator frequency. Analog ground. Reference voltage. The capacitor on this pin decouples the internal reference. A 0.1 mF capacitor needs to be connected between this pin and ground. PFC voltage feedback input. The voltage on this pin is compared to a 2.5 V reference (typical) to regulate the PFC output voltage. The voltage on this pin is also used to detect PFC undervoltage and overvoltage conditions. PFC regulator current sense input. A voltage ramp proportional to the PFC switch current is applied to this pin. The current sense threshold, VPCS(ILIM), is typically 0.84 V. A 110 ns (typical) leading edge blanking circuit filters the current sense signal at the start of each cycle. PFC inductor zero current detector. The inductor current is monitored using an auxiliary winding on the PFC inductor. The PFC drive signal is enabled during a high to low transition on the PZCD pin. A series resistor limits the current into the PZCD pin. PFC control voltage. This pin connects to the output of the PFC error amplifier. The error amplifier is a transconductance amplifier. A compensation network between this pin and grounds sets the PFC loop bandwidth. The PFC control voltage is compared to a level shifted version of VPCT to control the PFC duty ratio. PFC on time control capacitor. A 270 mA (typical) current source charges a capacitor connected between this pin and ground. Once the level shifted PCT voltage reaches VPControl, the PFC drive signal is disabled and the PCT capacitor is discharged. Positive input supply. This pin connects to an external capacitor for energy storage. An internal current source supplies current from HV to this pin. Once the VCC voltage reaches VCC(on) (15.3 V typical), the current source turns off and the controller is enabled. The current source turns on once VCC falls to VCC(off) (9.3 V typical). During normal operation, power is supplied to the IC via this pin by means of an auxiliary winding. Ground connection for PDRV and HDRVlo. Tie to the power stage return with a short trace. PFC switch gate drive control signal. The source and sink drive capability is limited to 60 W and 15 W (typical), respectively. A discrete driver may be needed to drive the external MOSFET. Half-bridge low side switch gate drive control signal. The source and sink drive capability is limited to 75 W and 15 W (typical), respectively. A discrete driver may be needed to drive the half bridge switch. Half-bridge high side driver source connection. This pin connects directly to the bridge terminal and can float up to 600 V. Half-bridge high side switch gate drive control signal. The source and sink drive capability is limited to 75 W and 15 W (typical), respectively. The supply terminals of the high side driver connect to the HBoost and HVS pins. Supply voltage of the high side gate driver. A charge pump generates a bootstrap voltage floating on top of the HVS voltage. A diode between the VCC and HBoost pins provides a charge path. The bootstrap voltage is VCC minus a diode drop.
4 5 6 7
2 3 4 5
OSC GND VREF PFB
8
6
PCS
9
7
PZCD
10
8
PControl
11
9
PCT
12
10
VCC
13 14 15
11 12 13
PGND PDRV HDRVlo
18 19
14 15
HVS HDRVhi
20
16
HBoost
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Table 2. MAXIMUM RATINGS (Notes 1 and 2)
Rating High Voltage Input Voltage High Voltage Input Current Supply Input Voltage Supply Input Current Oscillator Input Voltage Oscillator Input Current Bandgap Reference Decoupling Output Voltage Bandgap Reference Decoupling Output Current PFC Feedback Voltage Input Voltage PFC Feedback Voltage Input Current PFC Current Sense Input Voltage PFC Current Sense Input Current PFC Zero Current Detection Input Voltage PFC Zero Current Detection Input Current PFC Control Input Voltage PFC Control Input Current PFC On Time Control Input Voltage PFC On Time Control Input Current PFC Drive Signal Voltage PFC Drive Signal Current Half-Bridge Low Side Driver Input Voltage Half-Bridge Low Side Driver Input Current Half-Bridge High Side Driver Source Connection Input Voltage Half-Bridge High Side Driver Source Connection Input Current Half-Bridge High Side Driver Input Voltage Half-Bridge High Side Driver Input Current Half-Bridge High Side Driver Charge Pump Input Voltage Half-Bridge High Side Driver Charge Pump Input Current High Side Boost Circuit Supply Voltage (between HBoost and HVS pins) High Side Boost Circuit Supply Voltage (between HBoost and HVS pins) Half-Bridge High Side Driver Source Connection Slew Rate Operating Junction Temperature Storage Temperature Range Power Dissipation (TA = 25C, 1 Oz Cu, 0.155 Sq Inch, Printed Circuit Copper Clad) D Suffix, Plastic Package Case 751B-05 (SOIC-16) Thermal Resistance, Junction to Ambient (1 Oz Cu, 0.155 Sq Inch, Printed Circuit Copper Clad) D Suffix, Plastic Package Case 751B-05 (SOIC-16) Symbol VHV IHV VCC ICC VOSC IOSC VREF IREF VPFB IPFB VPCS IPCS VPZCD IPZCD VPControl IPControl VPCT IPCT VPDRV IPDRV VHDRVlo IHDRVlo VHVS IHVS VHDRVhi IHDRVhi VHBoost IHBoost VHBoost(supply) IHBoost(supply) dVHVS/dt TJ Tstg PD RJA Value -0.3 to 600 10 -0.3 to 20 10 -0.3 to 10 10 -0.3 to 9 10 -0.3 to 10 10 -0.3 to 10 10 -0.3 to 10 10 -0.3 to 10 1.2 -0.3 to 10 9 -0.3 to VCC 100 -0.3 to VCC 100 -1.0 to 600 100 -1.3 to 600 100 -0.3 to 600 100 -0.3 to VCC 100 TBD -40 to 150 -60 to 150 0.95 130 Unit V mA V mA V mA V mA V mA V mA V mA V mA V mA V mA V mA V mA V mA V mA V mA V/ns C C W C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. This device(s) contains ESD protection and exceeds the following tests: Pins 1, 14, 15 and 16 rated to the maximum voltage of the part, or 600 V. All Other Pins: Human Body Model 1500 V per JEDEC Standard JESD22-A114E. All Other Pins: Machine Model 150 V per JEDEC Standard JESD22-A115-A. 2. This device contains Latch-Up protection and exceeds 100 mA per JEDEC Standard JESD78.
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VPDRV = open, VHDRVlo = open, VHVS = 0 V, VHDRVhi = open, VHBoost = 15 V, COSC = 2200 pF, CVREF = 0.1 mF, CPCT = 1000 pF, for typical values TJ = 25C, for min/max values, TJ is -40C to 125C, unless otherwise noted) Characteristics STARTUP AND SUPPLY CIRCUITS Supply Voltage Startup Threshold Minimum Enable Threshold Minimum Operating Voltage Supply Current Device Disabled/Fault Device Switching Startup Current Startup Circuit Off-State Leakage Current BANDGAP REFERENCE Reference Voltage OSCILLATOR Half-Bridge Clock Frequency Maximum Half-Bridge Clock Frequency PFC ERROR AMPLIFIER PFC Feedback Voltage Reference 0C < TJ < 125C -40C < TJ < 125C PFC Feedback Voltage Reference Regulation with Line Error Amplifier Drive Capability Sink Source Open Loop Error Amplifier Transconductance Feedback Input Pulldown Current Source Error Amplifier Maximum Output Voltage Error Amplifier Minimum Output Voltage Error Amplifier Output Voltage Range VCC(on) + 0.2 V < VCC < 20 V VPREF(line) VPREF 2.42 2.40 -15 2.50 - - 2.58 2.60 15 mV mA VPControl = 4 V, VPFB = 5 V VPControl = 4 V, VPFB = 0.5 V VPControl = 4 V, VPFB = 2.4 V and 2.6 V VPFB = 3 V IPControl = 10 mA IPControl = -10 mA VEA(OH) - VEA(OL) IEA(SNK) IEA(SRC) Gm IPFB VEA(OH) VEA(OL) VEA 60 -60 60 0.5 5.30 2.10 3.1 80 -80 95 1.2 5.65 2.25 3.4 - - - 1.5 6.00 2.40 3.7 mS mA V V V V VHVS = 50 V COSC = open fclock fclock(MAX) 13.5 75 15.5 - 16.5 - kHz kHz CREF = 0.1 mF VREF 6.605 7.000 7.295 V V VCC Increasing VCC Decreasing VCC Decreasing VPFB = VPUVP(low) (Note 4) VCC = VCC (on) - 0.2 V, VHV = 50 V VHV = 600 V, VCC = VCC (on) + 0.2 V VCC(on) VCC(enable) VCC(off) ICC1 ICC2 Istart IHV(off) 14.3 13.6 8.5 1.0 1.5 3.0 - 15.3 14.6 9.3 1.4 2.4 7.5 15 16.3 15.6 10.0 mA 2.0 3.0 10.5 50 mA mA Conditions Symbol Min Typ Max Unit
Table 3. ELECTRICAL CHARACTERISTICS (VHV = open, VPFB = 2.4 V, VPCS = 0 V, VPZCD = 5 V, VPControl = open, VCC = 15 V,
3. Resistor/capacitor parallel combination (39 pF || 20 kW) between drive pin and driver supply and between xDRVxx and GND pins.
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VPDRV = open, VHDRVlo = open, VHVS = 0 V, VHDRVhi = open, VHBoost = 15 V, COSC = 2200 pF, CVREF = 0.1 mF, CPCT = 1000 pF, for typical values TJ = 25C, for min/max values, TJ is -40C to 125C, unless otherwise noted) Characteristics PFC CURRENT SENSE Current Sense Threshold Voltage Current Sense Input Bias Current Leading Edge Blanking Duration Propagation Delay PFC ZERO CURRENT DETECTION ZCD Threshold Voltage ZCD Voltage Hysteresis ZCD Input Bias Current PFC MAXIMUM OFF TIME Maximum Off Time PFC ON TIME RAMP GENERATOR ON time Capacitor Charge Current On Time Capacitor Discharge Time ON Time Capacitor Peak Voltage Minimum Duty Ratio Maximum On Time Detect Delay Voltage Delta between PControl Voltage Needed to Generate PDRV Pulses and VEA(OL) PFC OVERVOLTAGE and UNDERVOLTAGE Overvoltage Detector Threshold Voltage Overvoltage Comparator Hysteresis Midpoint between high and low threshold, VPControl = 4 V Between increasing and decreasing thresholds, VPControl = 4 V VPFB = VPREF + 1 V VPFB increasing VPFB decreasing VPFB increasing 10% to 90% (Note 4) 90% to 10% (Note 4) IPDRV = -8 mA IPDRV = 8 mA VPOVP VPOVP(HYS) 1.03* VPREF 5 1.05* VPREF 30 1.07* VPREF 60 V mV VPFB = 3.0 V, VPZCD = 0 V VPCT = VPCT(peak) + 1 V DVEA - VPCT(peak) VPCT = 0 V CPCT= 1 nF, VPCT = 2.4 V to 0.6 V IPCT(C) tPCT(D) VPCT(peak) DPMIN tPCT(delay) VPCT(offset) 220 - 2.6 0 - 250 270 70 3.0 - 250 400 300 300 3.4 - 375 550 mA ns V % ns mV tPFC(off) 50 180 350 ms VPZCD = 1 V VPZCD = 5 V VPZCD increasing VPZCD decreasing VZCD(high) VZCD(low) VZCD(HYS) IPZCD(bias1) IPZCD(bias2) 1.9 1.3 400 -1 -1 2.1 1.5 600 - - 2.3 1.7 800 1 1 V mV mA VPCS = VPCS(ILIM) + 1 V VPCS = 2 V VPCS(ILIM) IPCS tPCS(LEB) tPCS(delay) 0.78 -1 40 - 0.84 0 110 90 0.92 1 200 250 V mA ns ns Conditions Symbol Min Typ Max Unit
Table 4. ELECTRICAL CHARACTERISTICS (VHV = open, VPFB = 2.4 V, VPCS = 0 V, VPZCD = 5 V, VPControl = open, VCC = 15 V,
Propagation Delay Undervoltage Detector Threshold Voltage Undervoltage Comparator Hysteresis PFC DRIVER PFC Driver Rise Time PFC Driver Fall Time PFC Driver High State Voltage PFC Driver Low State Voltage
tPOVP(delay) VPUVP(high) VPUVP(low) VPUVP(HYS) tPDRV(rise) tPDRV(fall) VPDRV(OH) VPDRV(OL)
- - 175 20
400 290 230 60
800 350 - 100
ns mV mV
- - 14.00 -
18 9 14.55 0.12
- - - 0.50
ns ns V V
4. Resistor/capacitor parallel combination (39 pF || 20 kW) between PDRV and driver supply and between PDRV and GND pins.
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VPDRV = open, VHDRVlo = open, VHVS = 0 V, VHDRVhi = open, VHBoost = 15 V, COSC = 2200 pF, CVREF = 0.1 mF, CPCT = 1000 pF, for typical values TJ = 25C, for min/max values, TJ is -40C to 125C, unless otherwise noted) Characteristics HALF BRIDGE HIGH SIDE DRIVER Half-Bridge High Side Driver Rise Time Half-Bridge High Side Driver Fall Time High State Voltage Low State Voltage High Side Driver Duty Ratio Boost Supply Undervoltage Threshold Boost Current Consumption HVS Leakage Current HALF BRIDGE LOW SIDE DRIVER Half-Bridge Low Side Driver Rise Time Half-Bridge Low Side Driver Fall Time Half-Bridge Low Side Driver High State Voltage Half-Bridge Low Side Driver Low State Voltage Half-Bridge Low Side Driver Duty Ratio CROSSOVER DEAD TIME Delay from HDRVlo high to low to HDRVhi low to high transition Delay from HDRVhi high to low to HDRVlo low to high transition VHVS = 50 V VHVS = 50 V tHDRVhi(h-l) tHDRVhi(h-l) 500 500 785 785 950 950 ns ns 10% to 90% (Note 5) 90% to 10% (Note 5) IHDRVlo = -4 mA IHDRVlo = 4 mA 10 to 90% to 10% transitions (Note 5) tHDRVlo(rise) tHDRVhi(fall) VHDRVlo(OH) VHDRVlo(OL) DHDRVloMAX - - 14 - 44 18 9 14.7 0.06 48 - - - 0.5 50 ns ns V V % HDRVhi switching, between HDRVhi and HVS (Note 5) TJ = 25C, VHVS = 600 V, VHBoost = 600 V 10% to 90% (Note 5) 90% to 10% (Note 5) IHDRVhi = -4 mA IHDRVhi = 4 mA 10 to 90% to 10% transitions, VHSVS = 50 V (Note 5) tHDRVhi(rise) tHDRVhi(fall) VHDRVhi(OH) VHDRVhi(OL) DHDRVhiMAX VHBoost(UVLO) ICC(Boost) IHVS(off) - - 14.0 - 44 4 - - 18 9 14.7 0.06 48 6.1 0.1 0.1 - - - 0.5 50 8.0 0.5 1 ns ns V V % V mA mA Conditions Symbol Min Typ Max Unit
Table 5. ELECTRICAL CHARACTERISTICS (VHV = open, VPFB = 2.4 V, VPCS = 0 V, VPZCD = 5 V, VPControl = open, VCC = 15 V,
5. Resistor/capacitor parallel combination (39 pF || 20 kW) between drive pin and driver supply and between xDRVxx and GND pins.
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NCP1901
DETAILED OPERATING DESCRIPTION
Introduction
The NCP1901 is a combination of PFC and half-bridge resonant controllers optimized for off-line adapter applications. This device includes all the features needed to implement a highly efficient and small form factor adapter. It integrates a critical conduction mode (CrM) power factor correction (PFC) controller and half-bridge controller with a built-in 600 V driver. The half-bridge stage operates at a fixed frequency. Regulation is achieved by adjusting the PFC stage output voltage. This device includes an enable input, open feedback loop protection and PFC overvoltage and undervoltage detectors. Other features included in the NCP1901 are a 600 V startup circuit and an adjustable frequency oscillator. The controllers are properly sequenced, simplifying system design.
Supply Sequencing
remains disabled until the lower supply threshold, VCC(off), (typically 9.3 V) is reached. Once reached, the drive outputs are disabled and the startup current source is enabled. Once the outputs are disabled, the bias current of the NCP1901 is reduced, allowing VCC to charge back up. The supply capacitor provides power to the controller while operating in the power up or self-bias mode. During the converter power up, CCC must be sized such that a VCC voltage greater than VCC(off) is maintained while the auxiliary supply voltage is building up. Otherwise, VCC will collapse and the controller will turn off. The IC bias current and gate charge load at the drive outputs must be considered to correctly size CCC. The increase in current consumption due to external gate charge is calculated using Equation 1.
ICC(gate charge) + f @ QG
(eq. 1)
The PFC controller is enabled once VCC reaches VCC(on) and the PFB voltage exceeds VUVP(high), typically 290 mV. Once the PFC controller is enabled the PControl pin begins to charge. Once the control voltage exceeds VEA(OL) the first PFC drive pulse is observed. The half-bridge driver is enabled once the first PFC drive pulse is generated. This ensures a monotonic output voltage rise as the input voltage to the half bridge stage is regulated. The controller will not start in the event that VCC falls below VCC(MIN) before PFB goes above VUVP(high). This ensures there is enough time to start the controller before VCC reaches VCC(off).
Output Voltage Regulation
where, f is the operating frequency and QG is the gate charge of the external MOSFETs.
Main Oscillator
The oscillator frequency is set by the oscillator capacitor, COSC, on the OSC pin. The oscillator operates at a fixed 80% duty ratio. A current source charges COSC to its peak voltage, typically 5 V. Once the peak voltage is reached, the charge current is disabled and COSC is discharged down to 3 V by another current source. The charge and discharge currents are typically 173 and 692 mA, respectively. The oscillator frequency vs oscillator capacitance graph is shown in Figure 3.
fOSC, OSCILLATOR FREQUENCY (kHz) 100 90 80 70 60 50 40 30 20 10 0
The half-bridge stage operates at a fixed frequency. Output voltage regulation is achieved by adjusting the half-bridge input voltage (PFC output voltage). The PFC output voltage is sensed using a resistor divider. The mid point of the resistor divider connects to the PFB pin. Subtracting current out of the feedback resistor divider increases the PFC output voltage and thus regulation is achieved.
High Voltage Startup Circuit
The NCP1901 internal startup regulator eliminates the need for external startup components. In addition, this regulator increases the efficiency of the supply as it uses no power when in the normal mode of operation, but instead uses power supplied by an auxiliary winding. The startup regulator consists of a constant current source that supplies current from the high voltage line (Vin) to the supply capacitor on the VCC pin (CCC). The startup current (Istart) is typically 7.5 mA. The startup circuit is rated at a maximum voltage of 600 V. Once CCC is charged to 15.3 V (VCC(on)), the startup regulator is disabled and the PFC controller is enabled if the PFB voltage exceeds VPUVP(high). The startup regulator
400
800
1200
1600
2000
2400
COSC, OSCILLATOR CAPACITOR (pF)
Figure 3. Oscillator Frequency vs. Oscillator Capacitor
An internal clock signal is generated dividing by two the oscillator frequency. This clock signal is used to control the half-bridge controller. The half-bridge duty ratio is limited to 50%. The PFC is not synchronized to the oscillator as it operates in CrM.
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Voltage Reference
VDD > 5.65 V Clamp PControl < 2.25 V Clamp PFB IPFB VDD IPCT(C) PCT PFC Error Amplifier + - + - +
The internal voltage reference, VREF, is brought out of the controller to ease compensation requirements. The reference voltage is typically 7.0 V. A 0.1 mF is required for stability. The reference should not be loaded with external circuitry.
PFC Regulator
PZCD
ZCD Comparator
VZCD S Q Dominant Reset Latch Q R
The PFC stage operates in critical conduction mode (CrM). In CrM, the PFC inductor current, IL(t), reaches zero at the end of the switch cycle as shown in Figure 4. As seen in Figure 4, the average input current, Iin(t), is in phase with the ac line voltage, Vin(t).
+ -
VPREF On time Comparator Level Shifter + - PFC OVP Comparator - + PFCoff (eq. 3) (eq. 4)
+ PFC UVP VPOVP - Comparator + VPUVP - + - VCCGood
+ -
VPCS(ILIM)
Figure 4. Inductor Current in CrM
Figure 5. Constant On Time Control Block Diagram
High power factor is achieved in CrM by maintaining a constant on time (ton) for a given RMS input voltage (Vac(RMS)) and load conditions. Equation 2 shows the relationship between on time and system operating conditions.
ton + 2 @ P out @ L h @ Vac(RMS) 2
(eq. 2)
where, Pout is the output power, L is the PFC inductor inductance and h is the system efficiency.
On Time Control
The NCP1901 controls the on time by charging an external timing capacitor on the PCT pin, CT, with a constant current source, IPCT(C). The CT ramp is then compared to the control voltage, VPControl. The control voltage is constant for a given RMS line voltage and output load, satisfying Equation 2. A voltage offset, VPCT(offset), is added to the CT ramp to account for the control voltage range. The block diagram of the constant on time section is shown in Figure 5.
The PControl voltage is internally clamped between 2.25 V and 5.65 V. An offset voltage greater than the minimum PControl clamp voltage is added to the CT ramp prior to comparing it to the control voltage signal. This allows the PFC stage to stop the drive pulses (0% duty ratio) and regulate at light loads. The delta between the Pcontrol voltage needed to generate a PDRV pulse and the minimum PControl Clamp voltage is VPCT(offset). The timing capacitor is discharged and held low once the CT ramp voltage plus offset reaches VPControl. The PFC drive pulse terminates once the CT voltage reaches its peak voltage threshold, VPCT(peak). A new cycle starts once the inductor current reaches zero detected by a transition on the ZCD pin or the maximum off has been reached. The timing capacitor is sized such that the CT ramp peak voltage is reached at low line and full load. In this operating mode VPControl is at its maximum. Equation 3 is used to calculate the on time for a given CT.
ton(MAX) + C T @ V PCT(MAX) I PCT(C)
Substituting ton in Equation 2 with Equation 3 and rearranging Equation 4 provides a maximum value for CT.
CT w 2 @ P out @ L @ I PCT(C) h @ Vac(RMS) 2 @ VPCT(MAX)
where, VPCT(MAX), is the maximum PCT voltage, typically 3.0 V.
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+ -
PCS
LEB
PCS Comparator
NCP1901
Off Time Control
The PFC off time varies with the instantaneous line voltage and it is adjusted every cycle to allow the inductor current to reach zero before the next switch cycle begins. The inductor is demagnetized once its current reaches zero. Once the inductor is demagnetized the drain voltage of the PFC switch begins to drop. The inductor demagnetization is detected by sensing the voltage across the inductor using an auxiliary winding. This winding is commonly known as a zero crossing detector (ZCD) winding. This winding provides a scaled version of the inductor voltage. Figure 6 shows the ZCD winding arrangement.
timer is reset at the beginning of a PFC drive pulse and in a PFC undervoltage fault.
PFC Compensation
A transconductance error amplifier regulates the PFC output voltage, VPFC, by comparing the PFC feedback signal to an internal 2.5 V reference. As shown in Figure 28 a resistor divider from the PFC output voltage consisting of R1 and R2 generates the PFC feedback signal.
VPFC R1 PFC Error Amplifier - R2 IPFB - + VPREF +
PFB
Figure 8.
Figure 6. ZCD Winding Implementation
A negative voltage appears on the ZCD winding while the PFC switch is on. The PZCD voltage is positive while the PFC switch is off and current is flowing through the inductor. The PZCD voltage drops to and rings around zero volts once the inductor is demagnetized. Once a negative transition is detected in the PZCD pin the next switch cycle commences. A positive transition (corresponding to the PFC switch turn off) arms the ZCD detector to prevent false triggering. The arming of the ZCD detector is typically 2.1 V (VPZCD increasing) and the triggering is typically 1.5 V (VPZCD decreasing). The PZCD pin is internally clamped to 10 V with a zener diode. A resistor in series with the ZCD pin is required to limit the current into the PZCD pin. The zener diode prevents the voltage from exceeding the 10 V clamp or going below ground. Figure 7 shows typical ZCD waveforms.
Drain Voltage of PFC Switch PDRV 10 V VPZCD VZCD(high) VZCD(low) 0V
The feedback signal is applied to the amplifier inverting input. The internal 2.5 V reference, VPREF, is applied to the amplifier non-inverting input. The reference is trimmed during manufacturing to achieve an accuracy of 3.2%. Figure 5 shows the PFC error amplifier and sensing network. Equation 5 is used to calculate the values of the PFC feedback network.
VPFC + V PREF @ R1 ) R2 ) I PFB @ R1 R2
(eq. 5)
A transconductance amplifier has a voltage-to-current gain, gm. That is, the output current is controlled by the differential input voltage. The NCP1901 amplifier has a typical gm of 95 mS. The PControl pin provides access to the amplifier output for compensation. The compensation network is ground referenced allowing the PFC feedback signal to be used to detect an overvoltage condition. The compensation network on the PControl pin is selected to filter the bulk voltage ripple such that a constant control voltage is maintained across the ac line cycle. A capacitor between the PControl pin and ground sets a pole. A pole at or below 20 Hz is enough to filter the ripple voltage for a 50 and 60 Hz system. The low frequency pole, fp, of the system is calculated using Equation 6.
fp + gm 2pC PControl
(eq. 6)
Figure 7. ZCD Winding Waveforms
During startup there are no ZCD transitions to enable the PFC switch. A watchdog timer enables the PFC controller if no switch pulses are detected for a period of 180 ms (typical). The watchdog is also useful while operating at light load because the amplitude of the ZCD signal may be very small to cross the ZCD thresholds. The watchdog
where, CPControl is the capacitor on the PControl pin to ground. A key feature to using a transconductance type amplifier, is that the input is allowed to move independently with respect to the output, since the compensation capacitor is connected to ground. This allows dual usage of the feedback pin by the error amplifier and by the overvoltage comparator.
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NCP1901
PFC Undervoltage
The NCP1901 safely disables the controller if the PFB pin is left open. An undervoltage detector disables the controller if the voltage on the PFB pin is below VPUVP(low), typically 0.23 V. A 1.2 mA (typical) pull down current source, IPFB, ensures VPFB falls below VPUVP(low) if the PFB pin is floating. The PFB pull down current source affects the PFC output voltage regulation setpoint.
PFC Overvoltage
The half-bridge controller has a low side driver, HDRVlo, and a 600 V high side driver, HDRVhi. The built in high voltage driver eliminates the need for an external transformer or dedicated driver. A built-in delay between each drive transition eliminates the risk of cross conduction. The delay is typically 785 ns. The typical duty ratio of each half-bridge driver is 48%. The high side driver is connected between the HBoost and the HVS pins as shown in Figure 10.
An overvoltage detector monitors the PFC feedback voltage and disables the PFC driver if the PFC output voltage is greater than 5% of its nominal value. PFC drive pulses are suppressed until the overvoltage condition is removed. The overvoltage detector tolerance is better than 2% across the operating temperature voltage range. The overvoltage comparator hysteresis is typically 30 mV (1.2%).
PFC Overcurrent
The PFC current is monitored by means of an overcurrent detector. The PCS pin provides access to the overcurrent detector. The PFC drive pulse is terminated if the voltage on the PCS pin exceeds the overcurrent threshold, VPCS(ILIM). This comparison is done on a cycle by cycle basis. The overcurrent threshold is typically 0.84 V. The current sense signal is prone to leading edge spikes caused by the power switch transitions. The NCP1901 has leading edge blanking circuitry that blocks out the first 110 ns (typical) of each current pulse.
PFC Driver
Figure 10. Half-bridge High Side Driver
The PFC driver source and sink impedances are typically 60 and 15 W, respectively. Depending on the external MOSFET gate charge requirements, an external driver may be needed to drive the PFC power switch. A driver as the one shown in Figure 9 can be easily implemented.
A boost circuit comprised of Dboost and Cboost generates the supply voltage for the high side driver. Once HDRVlo turns on, the HVS pin is effectively grounded through the external power switch. This allows Cboost to charge to VCC. Once HDRVlo turns off, HVS floats high and Dboost is reversed biased. An undervoltage detector monitors the HBoost voltage. Once the HBoost voltage is greater than VBoost(UV), typically, 6.1 V, the high side driver is enabled. The low side driver generally starts before the high side driver because the boost voltage is generated by the low side driver switch transitions. The half-bridge low side driver source and sink impedances are typically 75 and 15 W, respectively. The half-bridge high side driver source and sink impedances are typically 75 and 15 W, respectively. Depending on the external MOSFETs gate charge requirements, an external driver may be needed to drive the low and high side power switches.
Analog and Power Ground
Figure 9. External Driver Half-Bridge Driver
The half-bridge stage operates at a fixed 50% duty ratio. The oscillator frequency is divided by two before it is applied to the half-bridge controller.
The NCP1901 has an analog ground, GND, and a power ground, PGND, terminal. GND is used for analog connections such as VREF and OSC. PGND is used for high current connections such as the gate drivers. It is recommended to have independent analog and power ground planes and connect them at a single point, preferably at the ground terminal of the system. This will prevent high current flowing on PGND from injecting noise in GND. The PGND connection should be as short and wide as possible to reduce inductance-induced spikes.
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NCP1901
PACKAGE DIMENSIONS
SO-20 WB CASE 751D-05 ISSUE G
D A
11 X 45 _
q
NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0_ 7_
H
M
B
M
20
10X
0.25
E
1
10
20X
B 0.25
M
B TA
S
B
S
A e
SEATING PLANE
h
18X
A1
T
C
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L
NCP1901
PACKAGE DIMENSIONS
SOIC-16 CASE 751B-05 ISSUE K
-A-
16
9
-B- P
1 8
8 PL
0.25 (0.010)
M
B
S
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
DIM A B C D F G J K M P R
0.25 (0.010)
TB
S
A
S
SOLDERING FOOTPRINT
6.40
16X 8X
1.12 16
1
16X
0.58
1.27 PITCH 8 9
DIMENSIONS: MILLIMETERS
The products described herein (NCP1901) may be covered by one or more of the following U.S. patents: 6,373,734. There may be other patents pending.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NCP1901/D

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